1. Field of the Invention
The present invention relates generally to the field of clock circuits, and specifically, to a method and apparatus for varying a clock frequency on a phase by phase basis.
2. Background Information
Component testers are often used to test and debug critical speed paths on newly designed microprocessors. A component tester is typically connected to the microprocessor and generates a test clock used to drive one or more functional units (also hereinafter referred to as the core) contained therein. The functional units include, for example, the data path, input units, execution units, cache, output units, and the like.
Clock shrinking is a mechanism by which the frequency of a clock (or group of clocks) is changed dynamically during the execution of a microprocessor. The term "shrinking" is used to denote that the frequency of a clock cycle of interest is reduced relative to other clock cycles. Clock shrinking is a debug tool for testing newly designed microprocessors and other types of integrated circuits. By shrinking a single clock (and leaving the other clocks at a lower, passing frequency), a single critical path can be isolated in a test or diagnostic that contains many critical speed paths.
Normally, in a high frequency microprocessor design, the core clock is generated from a phase-locked loop ("PLL"). The PLL is an analog circuit that generates a perfect, even duty cycle clock from an imperfect, uneven duty cycle clock across a wide range of process skews, voltages, and temperatures. The PLL also guarantees that the generated clock's rising edge is synchronized with the rising edge of the input clock. The PLL is used primarily to "clean up" a noisy, system bus clock before being driven to the microprocessor core as well as ensure that the core clock is still synchronized to the external clock.
FIG. 1 illustrates a prior art test system 100. The test system 100 includes a tester 110 coupled to a microprocessor 130 by way of signal line 120. Under test condition, the tester 110 transmits a test clock along signal line 120 to the microprocessor 130. The test clock typically includes one or more shrunk and/or stretched clocks for testing various functional units within the microprocessor 130. The test clock bypasses the PLL and drives the internal core clock directly. In this manner, a shrunk and/or stretched clock generated is passed directly into the functional units within the microprocessor. If the test clock is fed to the PLL, the PLL will attempt to "clean up" an intentional shrunk and/or stretched clock. The shrunk and/or stretched clock is treated as system noise and will either be re-adjusted back to the original frequency or break the lock of the PLL and cause it to spin out of control.
However, using an external tester to generate a varied clock and bypassing the PLL means that any system noise or inaccuracy is also passed directly into the core. For this reason, clock shrinking and/or stretching has only been possible on expensive component testers, which are capable of generating accurate, high frequency clocks. In recent years, however, the core frequency of microprocessors has been increasing at a faster rate than the capabilities of the component testers which makes it nearly impossible to provide an external clock at today's core frequencies.
Accordingly, there is a need in the technology for a method and apparatus for varying the clock frequency of one or more clocks on a cycle by cycle basis.